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IPPS
2007
IEEE
16 years 19 days ago
Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions
Parallel processing using multiple processors is a well-established technique to accelerate many different classes of applications. However, as the density of chips increases, ano...
Colin J. Ihrig, Justin Stander, Alex K. Jones
ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
15 years 10 months ago
Understanding the backward slices of performance degrading instructions
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
Craig B. Zilles, Gurindar S. Sohi
CIARP
2003
Springer
15 years 10 months ago
Uniclass and Multiclass Connectionist Classification of Dialogue Acts
Classification problems are traditionally focused on uniclass samples, that is, each sample of the training and test sets has one unique label, which is the target of the classific...
María José Castro Bleda, David Vilar...
IWMMDBMS
1996
67views more  IWMMDBMS 1996»
15 years 7 months ago
Reducing Initial Latency in a Multimedia Storage System
A multimedia server delivers presentations (e.g., videos, movies, games), providing high bandwidth and continuous real-time delivery. In this paper we present techniques for reduc...
Edward Y. Chang, Hector Garcia-Molina
CODES
2010
IEEE
15 years 4 months ago
A greedy buffer allocation algorithm for power-aware communication in body sensor networks
Monitoring human movements using wireless sensory devices promises to revolutionize the delivery of healthcare services. In spite of their potentials for many application domains,...
Hassan Ghasemzadeh, Roozbeh Jafari