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ICCAD
2006
IEEE
147views Hardware» more  ICCAD 2006»
16 years 3 months ago
Analysis and modeling of CD variation for statistical static timing
Statistical static timing analysis (SSTA) has become a key method for analyzing the effect of process variation in aggressively scaled CMOS technologies. Much research has focused...
Brian Cline, Kaviraj Chopra, David Blaauw, Yu Cao
ICDM
2005
IEEE
190views Data Mining» more  ICDM 2005»
16 years 5 days ago
Neighborhood Formation and Anomaly Detection in Bipartite Graphs
Many real applications can be modeled using bipartite graphs, such as users vs. files in a P2P system, traders vs. stocks in a financial trading system, conferences vs. authors ...
Jimeng Sun, Huiming Qu, Deepayan Chakrabarti, Chri...
TSE
2008
165views more  TSE 2008»
15 years 6 months ago
A Systematic Study of Failure Proximity
Software end users are the best testers, who keep revealing bugs in software that has undergone rigorous in-house testing. In order to leverage their testing efforts, failure repor...
Chao Liu 0001, Xiangyu Zhang, Jiawei Han
NOCS
2009
IEEE
16 years 1 months ago
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
This paper presents a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedd...
Anh T. Tran, Dean Truong, Bevan M. Baas
GLVLSI
2003
IEEE
119views VLSI» more  GLVLSI 2003»
15 years 12 months ago
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...