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FPGA
2008
ACM
155views FPGA» more  FPGA 2008»
15 years 8 months ago
A novel FPGA logic block for improved arithmetic performance
To improve FPGA performance for arithmetic circuits, this paper proposes a new architecture for FPGA logic cells that includes a 6:2 compressor. The new cell features additional f...
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
IADIS
2004
15 years 8 months ago
A mobile-aware business logic container
Currently providing such features in mobile applications as the sending of lower-bandwidth images when a client device is in a low-bandwidth access area, the business logic to dis...
Robert Steele, Elaine Lawrence
CONCUR
2003
Springer
16 years 22 hour ago
Comparative Branching-Time Semantics
d Abstract) Christel Baier1 , Holger Hermanns2,3 , Joost-Pieter Katoen2 , and Verena Wolf1 1 Institut f¨ur Informatik I, University of Bonn R¨omerstraße 164, D-53117 Bonn, Germa...
Christel Baier, Holger Hermanns, Joost-Pieter Kato...
DSD
2004
IEEE
136views Hardware» more  DSD 2004»
15 years 10 months ago
FPGA Based Design of the Railway's Interlocking Equipments
This paper describes the architecture of a safety system of the railway's interlocking equipment, which has been developed for Czech railways. The system will be used for the...
Radek Dobias, Hana Kubatova
UAI
2003
15 years 8 months ago
Implementation and Comparison of Solution Methods for Decision Processes with Non-Markovian Rewards
This paper examines a number of solution methods for decision processes with non-Markovian rewards (NMRDPs). They all exploit a temporal logic specification of the reward functio...
Charles Gretton, David Price, Sylvie Thiéba...