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ICCD
2001
IEEE
119views Hardware» more  ICCD 2001»
16 years 3 months ago
A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage
We present a simulation-based semi-formal verification method for sequential circuits described at the registertransfer level. The method consists of an iterative loop where cove...
Serdar Tasiran, Farzan Fallah, David G. Chinnery, ...
ICCAD
2008
IEEE
89views Hardware» more  ICCAD 2008»
16 years 3 months ago
Temperature aware task sequencing and voltage scaling
Abstract—On-chip power density and temperature are rising exponentially with decreasing feature sizes. This alarming trend calls for temperature management at every level of syst...
Ramkumar Jayaseelan, Tulika Mitra
ICCAD
2006
IEEE
111views Hardware» more  ICCAD 2006»
16 years 3 months ago
State re-encoding for peak current minimization
In a synchronous finite state machine (FSM), huge current peaks are often observed at the moment of state transition. Previous low power state encoding algorithms focus on the red...
Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
ICCAD
2005
IEEE
107views Hardware» more  ICCAD 2005»
16 years 3 months ago
Projection-based performance modeling for inter/intra-die variations
Large-scale process fluctuations in nano-scale IC technologies suggest applying high-order (e.g., quadratic) response surface models to capture the circuit performance variations....
Xin Li, Jiayong Le, Lawrence T. Pileggi, Andrzej J...
ICCAD
2005
IEEE
168views Hardware» more  ICCAD 2005»
16 years 3 months ago
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
— Process variations cause significant timing uncertainty and yield degradation in deep sub-micron technologies. A solution to counter timing uncertainty is post-silicon clock t...
Jeng-Liang Tsai, Lizheng Zhang
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