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194
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CF
2007
ACM
15 years 10 months ago
2007
ACM
This paper presents a novel architectural technique to hide fetch latency overhead of hardware encrypted and authenticated memory. A number of recent secure processor designs have...
174
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PPOPP
2009
ACM
16 years 7 months ago
2009
ACM
Transactional Memory (TM) is being studied widely as a new technique for synchronizing concurrent accesses to shared memory data structures for use in multi-core systems. Much of ...
151
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SPAA
2009
ACM
16 years 7 months ago
2009
ACM
Transactional memory (TM) is a promising approach for designing concurrent data structures, and it is essential to develop better understanding of the formal properties that can b...
159
Voted
HPCA
2008
IEEE
16 years 7 months ago
2008
IEEE
Simultaneous Multithreading (SMT) attempts to keep a dynamically scheduled processor's resources busy with work from multiple independent threads. Threads with longlatency st...
165
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HPCA
2006
IEEE
16 years 7 months ago
2006
IEEE
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buf...