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DAC
2009
ACM
15 years 11 months ago
Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators
Dynamic binary translation (DBT) can be used to address important issues in embedded systems. DBT systems store translated code in a software-managed code cache. Unlike general-pu...
José Baiocchi, Bruce R. Childers
HPCA
2000
IEEE
15 years 11 months ago
Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors
We consider a variety of dynamic, hardware-based methods for exploiting load/store parallelism, including mechanisms that use memory dependence speculation. While previous work ha...
Andreas Moshovos, Gurindar S. Sohi
ICNP
1999
IEEE
15 years 11 months ago
Dynamic Memory Model Based Framework for Optimization of IP Address Lookup Algorithms
The design of software-based algorithms for fast IP address lookup targeted for general purpose processors has received tremendous attention in recent years due to its low cost im...
Gene Cheung, Steven McCanne
ARITH
1993
IEEE
15 years 11 months ago
An accurate LNS arithmetic unit using interleaved memory function interpolator
This paper describes a logarithmic number system (LNS) arithmetic unit using a new methodfor polynomial interpolation in hardware. The use of an interleaved memory reduces storage...
David M. Lewis
DAC
2011
ACM
14 years 6 months ago
Rethinking memory redundancy: optimal bit cell repair for maximum-information storage
SRAM design has been a major challenge for nanoscale manufacturing technology. We propose a new bit cell repair scheme for designing maximum-information memory system (MIMS). Unli...
Xin Li