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CF
2009
ACM
16 years 1 months ago
A light-weight fairness mechanism for chip multiprocessor memory systems
Chip Multiprocessor (CMP) memory systems suffer from the effects of destructive thread interference. This interference reduces performance predictability because it depends heavil...
Magnus Jahre, Lasse Natvig
HPCA
1995
IEEE
15 years 10 months ago
Program Balance and Its Impact on High Performance RISC Architectures
Information on the behavior of programs is essential for deciding the number and nature of functional units in high performance architectures. In this paper, we present studies on...
Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee...
APSCC
2008
IEEE
15 years 8 months ago
Optimizing the Execution Time of the SLA-based Workflow in the Grid with Parallel Processing Technology
Service Level Agreements (SLAs) is currently one of the major research topics in Grid Computing. Among many system components for the supporting of SLA-aware Gridbased workflow, t...
Dang Minh Quan, Jörn Altmann, Laurence Tianru...
MICRO
2009
IEEE
222views Hardware» more  MICRO 2009»
16 years 1 months ago
Qilin: exploiting parallelism on heterogeneous multiprocessors with adaptive mapping
Heterogeneous multiprocessors are growingly important in the multi-core era due to their potential for high performance and energy efficiency. In order for software to fully real...
Chi-Keung Luk, Sunpyo Hong, Hyesoon Kim
SC
2003
ACM
15 years 12 months ago
Identifying and Exploiting Spatial Regularity in Data Memory References
The growing processor/memory performance gap causes the performance of many codes to be limited by memory accesses. If known to exist in an application, strided memory accesses fo...
Tushar Mohan, Bronis R. de Supinski, Sally A. McKe...