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DATE
2008
IEEE
133views Hardware» more  DATE 2008»
16 years 1 months ago
Memory Organization with Multi-Pattern Parallel Accesses
We propose an interleaved memory organization supporting multi-pattern parallel accesses in twodimensional (2D) addressing space. Our proposal targets computing systems with high ...
Arseni Vitkovski, Georgi Kuzmanov, Georgi Gaydadji...
RTCSA
2008
IEEE
16 years 1 months ago
Providing Memory QoS Guarantees for Real-Time Applications
Nowadays, systems often integrate a variety of applications whose service requirements are heterogeneous. Consequently, systems must be able to concurrently serve applications whi...
Audrey Marchand, Patricia Balbastre, Ismael Ripoll...
ICESS
2007
Springer
16 years 25 days ago
An Efficient Buffer Management Scheme for Implementing a B-Tree on NAND Flash Memory
Recently, NAND flash memory has been used for a storage device in various mobile computing devices such as MP3 players, mobile phones and laptops because of its shock-resistant, lo...
Hyun-Seob Lee, Sangwon Park, Ha-Joo Song, Dong-Ho ...
WMPI
2004
ACM
16 years 2 days ago
SCIMA-SMP: on-chip memory processor architecture for SMP
Abstract. In this paper, we propose a processor architecture with programmable on-chip memory for a high-performance SMP (symmetric multi-processor) node named SCIMA-SMP (Software ...
Chikafumi Takahashi, Masaaki Kondo, Taisuke Boku, ...
ICCS
2003
Springer
15 years 12 months ago
Exploiting Stability to Reduce Time-Space Cost for Memory Tracing
Memory traces record the addresses touched by a program during its execution, enabling many useful investigations for understanding and predicting program performance. But complete...
Xiaofeng Gao, Allan Snavely