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IPPS
2010
IEEE
15 years 4 months ago
A PRAM-NUMA model of computation for addressing low-TLP workloads
It is possible to implement the parallel random access machine (PRAM) on a chip multiprocessor (CMP) efficiently with an emulated shared memory (ESM) architecture to gain easy par...
Martti Forsell
ISCA
1995
IEEE
118views Hardware» more  ISCA 1995»
15 years 10 months ago
The EM-X Parallel Computer: Architecture and Basic Performance
Latency tolerance is essential in achieving high performance on parallel computers for remote function calls and fine-grained remote memory accesses. EM-X supports interprocessor ...
Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Ha...
CCS
2008
ACM
15 years 8 months ago
BootJacker: compromising computers using forced restarts
BootJacker is a proof-of-concept attack tool which demonstrates that authentication mechanisms employed by an operating system can be bypassed by obtaining physical access and sim...
Ellick Chan, Jeffrey C. Carlyle, Francis M. David,...
CHI
2005
ACM
16 years 6 months ago
Interrupted cognition and design for non-disruptiveness: the skilled memory approach
Interruptions have gained in importance as a topic in current HCI research. Through a series of experiments, we take a step toward analyzing the active role of human memory in con...
Antti Oulasvirta
HPCA
1995
IEEE
15 years 10 months ago
Access Ordering and Memory-Conscious Cache Utilization
As processor speeds increase relative to memory speeds, memory bandwidth is rapidly becoming the limiting performance factor for many applications. Several approaches to bridging ...
Sally A. McKee, William A. Wulf