10805 search results - page 115 / 2161 » Mapping Computation with No Memory |
174
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ASPLOS
2010
ACM
16 years 1 months ago
2010
ACM
We present a general scheme for virtualizing main memory errorcorrection mechanisms, which map redundant information needed to correct errors into the memory namespace itself. We ...
158
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CODES
2005
IEEE
16 years 1 days ago
2005
IEEE
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
146
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ISCA
2000
IEEE
15 years 10 months ago
2000
IEEE
Spatial-lattice computations with finite-range interactions are an important class of easily parallelized computations. This class includes many simple and direct algorithms for ...
176
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ICS
2009
Tsinghua U.
16 years 1 months ago
2009
Tsinghua U.
The Cell BE is a multicore processor with eight vector accelerators (called SPEs) that implement explicit cache management through direct memory access engines. While the Cell has...
210
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AINA
2007
IEEE
15 years 8 months ago
2007
IEEE
— We present an augmented map interface called Phygital (physical, digital) Map that enables users to access digital multimedia stored in various off-the-shelf devices from physi...