3373 search results - page 515 / 675 » Malleable applications for scalable high performance computi... |
190
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TC
2008
15 years 6 months ago
2008
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...
184
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CASES
2005
ACM
15 years 8 months ago
2005
ACM
Interconnection networks have been deployed as the communication fabric in a wide range of parallel computer systems. With recent technological trends allowing growing quantities ...
178
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ICS
2009
Tsinghua U.
16 years 1 months ago
2009
Tsinghua U.
In this work, we propose a new FPGA design flow that combines the CUDA programming model from Nvidia with the state of the art high-level synthesis tool AutoPilot from AutoESL, to...
187
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DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
—Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low comput...
195
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CLUSTER
2003
IEEE
15 years 12 months ago
2003
IEEE
In this paper we analyze the I/O access patterns of a widely-used biological sequence search tool and implement two variations that employ parallel-I/O for data access based on PV...