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ASAP
2005
IEEE
169views Hardware» more  ASAP 2005»
16 years 9 days ago
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
Grigoris Dimitroulakos, Michalis D. Galanis, Costa...
WMPI
2004
ACM
16 years 2 days ago
Memory coherence activity prediction in commercial workloads
Abstract. Recent research indicates that prediction-based coherence optimizations offer substantial performance improvements for scientific applications in distributed shared memor...
Stephen Somogyi, Thomas F. Wenisch, Nikolaos Harda...
HPCA
2008
IEEE
16 years 7 months ago
An OS-based alternative to full hardware coherence on tiled CMPs
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
Christian Fensch, Marcelo Cintra
ICDCS
2009
IEEE
16 years 3 months ago
Down the Block and Around the Corner The Impact of Radio Propagation on Inter-vehicle Wireless Communication
Vehicular networks are emerging as a new distributed system environment with myriad possible applications. Most studies on vehicular networks are carried out via simulation, given...
John S. Otto, Fabián E. Bustamante, Randall...
SAC
2010
ACM
16 years 1 months ago
Extraction of component-environment interaction model using state space traversal
Scalability of software engineering methods can be improved by application of the methods to individual components instead of complete systems. This is, however, possible only if ...
Pavel Parizek, Nodir Yuldashev