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ANCS
2007
ACM
15 years 10 months ago
Low-latency scheduling in large switches
Scheduling in large switches is challenging. Arbiters must operate at high rates to keep up with the high switching rates demanded by multi-gigabit-per-second link rates and short...
Wladek Olesinski, Nils Gura, Hans Eberle, Andres M...
164
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ARCS
2006
Springer
15 years 10 months ago
A Single Issue DSP based Multi-standard Media Processor for Mobile Platforms
: This paper presents the study of modifying a legacy single-issue DSP processor to provide real-time processing capacity for emerging multimedia applications. The latest video com...
Di Wu, Tiejun Hu, Dake Liu
IMS
2000
125views Hardware» more  IMS 2000»
15 years 10 months ago
Compiler-Directed Cache Line Size Adaptivity
The performance of a computer system is highly dependent on the performance of the cache memory system. The traditional cache memory system has an organization with a line size tha...
Dan Nicolaescu, Xiaomei Ji, Alexander V. Veidenbau...
SIGCOMM
2004
ACM
16 years 5 days ago
Work-conserving distributed schedulers for Terabit routers
−Buffered multistage interconnection networks offer one of the most scalable and cost-effective approaches to building high capacity routers. Unfortunately, the performance of su...
Prashanth Pappu, Jonathan S. Turner, Kenneth Wong
GECCO
2007
Springer
207views Optimization» more  GECCO 2007»
16 years 28 days ago
A data parallel approach to genetic programming using programmable graphics hardware
In recent years the computing power of graphics cards has increased significantly. Indeed, the growth in the computing power of these graphics cards is now several orders of magn...
Darren M. Chitty