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MICRO
2008
IEEE
136views Hardware» more  MICRO 2008»
16 years 27 days ago
Power to the people: Leveraging human physiological traits to control microprocessor frequency
Any architectural optimization aims at satisfying the end user. However, modern architectures execute with little to no knowledge about the individual user. If architectures could...
Alex Shye, Yan Pan, Benjamin Scholbrock, J. Scott ...
NSPW
2006
ACM
16 years 13 days ago
Large-scale collection and sanitization of network security data: risks and challenges
Over the last several years, there has been an emerging interest in the development of widearea data collection and analysis centers to help identify, track, and formulate respons...
Phillip A. Porras, Vitaly Shmatikov
ICS
2004
Tsinghua U.
15 years 12 months ago
CQoS: a framework for enabling QoS in shared caches of CMP platforms
Cache hierarchies have been traditionally designed for usage by a single application, thread or core. As multi-threaded (MT) and multi-core (CMP) platform architectures emerge and...
Ravi R. Iyer
ESOP
2001
Springer
15 years 11 months ago
Modeling an Algebraic Stepper
Programmers rely on the correctness of the tools in their programming environments. In the past, semanticists have studied the correctness of compilers and compiler analyses, which...
John Clements, Matthew Flatt, Matthias Felleisen
MICRO
1999
IEEE
105views Hardware» more  MICRO 1999»
15 years 10 months ago
DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design
Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that ...
Todd M. Austin