This paper describes a compiler for stream programs that efficiently schedules computational kernels and stream memory operations, and allocates on-chip storage. Our compiler uses...
As chip multiprocessors (CMPs) become increasingly mainstream, architects have likewise become more interested in how best to share a cache hierarchy among multiple simultaneous t...
Lisa R. Hsu, Steven K. Reinhardt, Ravishankar R. I...
Transactional memory is an attractive design concept for scalable multiprocessors because it offers efficient lock-free synchronization and greatly simplifies parallel software....
— The limited number of orthogonal channels and the autonomous installations of hotspots and home wireless networks often leave neighboring 802.11 basic service sets (BSS’s) op...
Chun-cheng Chen, Eunsoo Seo, Hwangnam Kim, Haiyun ...
− In a clustered, multi-hop sensor network, a large number of inexpensive, geographically-distributed sensor nodes each use their observations of the environment to make local ha...