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ISCA
2011
IEEE
290views Hardware» more  ISCA 2011»
14 years 10 months ago
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks
To meet the demand for more powerful high-performance shared-memory servers, multiprocessor systems must incorporate efficient and scalable cache coherence protocols, such as thos...
Blas Cuesta, Alberto Ros, María Engracia G&...
ICSR
2011
Springer
14 years 10 months ago
Improving Product Line Architecture Design and Customization by Raising the Level of Variability Modeling
Product Line Architecture (PLA) plays a central role in software product line development. In order to support architecture-level variability modeling, most architecture descriptio...
Jiayi Zhu, Xin Peng, Stan Jarzabek, Zhenchang Xing...
MOBISYS
2011
ACM
14 years 9 months ago
AccuLoc: practical localization of performance measurements in 3G networks
Operators of 3G data networks need to distinguish the performance of each geographic area in their 3G networks to detect and resolve local network problems. This is because the qu...
Qiang Xu, Alexandre Gerber, Zhuoqing Morley Mao, J...
ANCS
2011
ACM
14 years 6 months ago
A Scalability Study of Enterprise Network Architectures
The largest enterprise networks already contain hundreds of thousands of hosts. Enterprise networks are composed of Ethernet subnets interconnected by IP routers. These routers re...
Brent Stephens, Alan L. Cox, Scott Rixner, T. S. E...
DSN
2011
IEEE
14 years 6 months ago
Transparent dynamic binding with fault-tolerant cache coherence protocol for chip multiprocessors
—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...
Shuchang Shan, Yu Hu, Xiaowei Li