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ISCA
2005
IEEE
115views Hardware» more  ISCA 2005»
16 years 13 days ago
The V-Way Cache: Demand Based Associativity via Global Replacement
As processor speeds increase and memory latency becomes more critical, intelligent design and management of secondary caches becomes increasingly important. The efficiency of curr...
Moinuddin K. Qureshi, David Thompson, Yale N. Patt
ISCAS
2005
IEEE
158views Hardware» more  ISCAS 2005»
16 years 13 days ago
Designing optimized pipelined global interconnects: algorithms and methodology impact
— As across-chip wire delays exceed a clock cycle, interconnect pipelining becomes essential. However, the arbitrary insertion of flip-flops can change the differentials of lat...
Vidyasagar Nookala, Sachin S. Sapatnekar
ISCAS
2005
IEEE
177views Hardware» more  ISCAS 2005»
16 years 13 days ago
A combined two's complement and floating-point comparator
— This paper presents the design of a combined two’s complement and IEEE 754-compliant floating-point comparator. Unlike previous designs, this comparator incorporates both op...
James E. Stine, Michael J. Schulte
ISCAS
2005
IEEE
147views Hardware» more  ISCAS 2005»
16 years 13 days ago
A two-chip, 4-MHz, microelectromechanical reference oscillator
— The paper describes a 4-MHz temperature compensated reference oscillator based on a capacitive silicon micro-mechanical resonator. The design of the resonator has been optimize...
Krishnakumar Sundaresan, Paul S. Ho, Siavash Pourk...
144
Voted
ISCAS
2005
IEEE
133views Hardware» more  ISCAS 2005»
16 years 13 days ago
Sub-sequence video coding for improved temporal scalability
—Compression efficiency and bitrate scalability are among the key factors in video coding. The paper introduces novel sub-sequence coding techniques for temporal scalability. The...
Dong Tian, Miska M. Hannuksela, Moncef Gabbouj