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DATE
2010
IEEE
154views Hardware» more  DATE 2010»
15 years 11 months ago
ERSA: Error Resilient System Architecture for probabilistic applications
There is a growing concern about the increasing vulnerability of future computing systems to errors in the underlying hardware. Traditional redundancy techniques are expensive for...
Larkhoon Leem, Hyungmin Cho, Jason Bau, Quinn A. J...
DATE
2010
IEEE
149views Hardware» more  DATE 2010»
15 years 11 months ago
Integrated end-to-end timing analysis of networked AUTOSAR-compliant systems
—As Electronic Control Units (ECUs) and embedded software functions within an automobile keep increasing in number, the scale and complexity of automotive embedded systems is gro...
Karthik Lakshmanan, Gaurav Bhatia, Ragunathan Rajk...
GLVLSI
2010
IEEE
210views VLSI» more  GLVLSI 2010»
15 years 11 months ago
Overscaling-friendly timing speculation architectures
Processors have traditionally been designed for the worst-case, resulting in designs that have high yields, but are expensive in terms of area and power. Better-than-worst-case (B...
John Sartori, Rakesh Kumar
ISCA
2010
IEEE
170views Hardware» more  ISCA 2010»
15 years 11 months ago
Relax: an architectural framework for software recovery of hardware faults
As technology scales ever further, device unreliability is creating excessive complexity for hardware to maintain the illusion of perfect operation. In this paper, we consider whe...
Marc de Kruijf, Shuou Nomura, Karthikeyan Sankaral...
ISCA
2010
IEEE
181views Hardware» more  ISCA 2010»
15 years 11 months ago
ColorSafe: architectural support for debugging and dynamically avoiding multi-variable atomicity violations
In this paper, we propose ColorSafe, an architecture that detects and dynamically avoids single- and multi-variable atomicity violation bugs. The key idea is to group related data...
Brandon Lucia, Luis Ceze, Karin Strauss
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