3729 search results - page 531 / 746 » METRICS: a system architecture for design process optimizati... |
191
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CODES
2007
IEEE
16 years 1 months ago
2007
IEEE
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
187
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DAC
2000
ACM
16 years 7 months ago
2000
ACM
The Esprit/OMI-COSY project defines transaction-levels to set-up the exchange of IP's in separating function from architecture and body-behavior from proprietary interfaces. ...
164
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DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
-- Starting Electronic System Level (ESL) design flows with executable High-Level Models (HLMs) has the potential to sustainably improve productivity. However, writing good HLMs fo...
184
Voted
DATE
2010
IEEE
15 years 4 months ago
2010
IEEE
Topology virtualization techniques are proposed for NoCbased many-core processors with core-level redundancy to isolate hardware changes caused by on-chip defective cores. Prior w...
159
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DATE
2005
IEEE
16 years 8 days ago
2005
IEEE
: - One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at...