3729 search results - page 420 / 746 » METRICS: a system architecture for design process optimizati... |
177
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
211
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INFORMATICALT
2007
15 years 6 months ago
2007
The innovations and improvements in digital imaging sensors and scanners, computer modeling, haptic equipments and e-learning technology, as well as the availability of many powerf...
189
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SPAA
2009
ACM
16 years 7 months ago
2009
ACM
Designing an overlay network for publish/subscribe communication in a system where nodes may subscribe to many different topics of interest is of fundamental importance. For scala...
196
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HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
184
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ISPASS
2009
IEEE
16 years 1 months ago
2009
IEEE
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...