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ANCS
2007
ACM
15 years 10 months ago
Towards high-performance flow-level packet processing on multi-core network processors
There is a growing interest in designing high-performance network devices to perform packet processing at flow level. Applications such as stateful access control, deep inspection...
Yaxuan Qi, Bo Xu, Fei He, Baohua Yang, Jianming Yu...
ASPDAC
2004
ACM
109views Hardware» more  ASPDAC 2004»
16 years 6 days ago
Design methodology for IRA codes
Channel coding is an important building block in communication systems since it ensures the quality of service. Irregular repeat-accumulate (IRA) codes belong to the class of Low-...
Frank Kienle, Norbert Wehn
DATE
1997
IEEE
95views Hardware» more  DATE 1997»
15 years 11 months ago
Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications
A design methodology for the synthesis of digital circuits used in high throughput digital modems is presented. The methodology spans digital modem design from the link level to t...
Patrick Schaumont, Serge Vernalde, Luc Rijnders, M...
ISCAS
1994
IEEE
138views Hardware» more  ISCAS 1994»
15 years 11 months ago
High-Throughput Data Compressor Designs Using Content Addressable Memory
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
Ren-Yang Yang, Chen-Yi Lee
IEE
2007
100views more  IEE 2007»
15 years 6 months ago
Designing and constructing modifiable middleware using component frameworks
Because of the increasingly diverse and dynamic environments in which they must operate, modern middleware platforms need to explicitly support modifiability. Modifiability should...
Nikos Parlavantzas, Geoffrey Coulson