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DATE
2005
IEEE
110views Hardware» more  DATE 2005»
16 years 12 days ago
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
The increasing complexity and the short life cycles of embedded systems are pushing the current system-onchip designs towards a rapid increasing on the number of programmable proc...
Alexandre M. Amory, Marcelo Lubaszewski, Fernando ...
CODES
2005
IEEE
16 years 12 days ago
DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs
We present a new scheme for dynamic voltage and frequency scaling (DVS) for processing multimedia streams on architectures with restricted buffer sizes. The main advantage of our ...
Alexander Maxiaguine, Samarjit Chakraborty, Lothar...
ASPDAC
2005
ACM
104views Hardware» more  ASPDAC 2005»
15 years 8 months ago
Speed and voltage selection for GALS systems based on voltage/frequency islands
Due to increasing clock speeds and shrinking technologies, distributing a single global clock signal throughout a chip is becoming a difficult and challenging proposition. In this...
Koushik Niyogi, Diana Marculescu
CORR
2006
Springer
103views Education» more  CORR 2006»
15 years 6 months ago
VXA: A Virtual Architecture for Durable Compressed Archives
Data compression algorithms change frequently, and obsolete decoders do not always run on new hardware and operating systems, threatening the long-term usability of content archiv...
Bryan Ford
161
Voted
TOG
2010
157views more  TOG 2010»
15 years 1 months ago
Computer-generated residential building layouts
We present a method for automated generation of building layouts for computer graphics applications. Our approach is motivated by the layout design process developed in architectu...
Paul Merrell, Eric Schkufza, Vladlen Koltun