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ICIP
1997
IEEE
16 years 8 months ago
Zerotree Design for Image Compression: Toward Weighted Universal Zerotree Coding
Weconsidertheproblem of optimal, data-dependentzerotree designfor use in weighted universal zerotree codes for image compression.A weighted universalzerotree code (WUZC) is a data...
Michelle Effros
ASPLOS
1989
ACM
15 years 10 months ago
Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...
Robert Cohn, Thomas R. Gross, Monica S. Lam, P. S....
DATE
2006
IEEE
128views Hardware» more  DATE 2006»
16 years 24 days ago
Efficient link capacity and QoS design for network-on-chip
This paper addresses the allocation of link capacities in the automated design process of a network-on-chip based system. Communication resource costs are minimized under Quality-...
Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israe...
197
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WWW
2005
ACM
16 years 7 months ago
A multi-threaded PIPELINED Web server architecture for SMP/SoC machines
Design of high performance Web servers has become a recent research thrust to meet the increasing demand of networkbased services. In this paper, we propose a new Web server archi...
Gyu Sang Choi, Jin-Ha Kim, Deniz Ersoz, Chita R. D...
DAC
1994
ACM
15 years 10 months ago
Performance-Driven Simultaneous Place and Route for Row-Based FPGAs
Sequential place and route tools for FPGAs are inherently weak at addressing both wirability and timing optimizations. This is primarily due to the difficulty in predicting these ...
Sudip Nag, Rob A. Rutenbar