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ICCAD
1996
IEEE
77views Hardware» more  ICCAD 1996»
15 years 10 months ago
Power optimization in disk-based real-time application specific systems
While numerous power optimization techniques have been at all levels of design process abstractions for electronic components, until now, power minimization in mixed mechanical-el...
Inki Hong, Miodrag Potkonjak
ICCAD
2008
IEEE
150views Hardware» more  ICCAD 2008»
16 years 3 months ago
Performance estimation and slack matching for pipelined asynchronous architectures with choice
— This paper presents a fast analytical method for estimating the throughput of pipelined asynchronous systems, and then applies that method to develop a fast solution to the pro...
Gennette Gill, Vishal Gupta, Montek Singh
VLSID
2003
IEEE
78views VLSI» more  VLSID 2003»
16 years 7 months ago
Interface Design Techniques for Single-Chip Systems
This paper quantifies the performance of typical functional unit interface designs in single-chip systems. We introduce a specific equation to guide the design of optimal module i...
Robert H. Bell Jr., Lizy Kurian John
DAC
2003
ACM
16 years 7 months ago
Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system
This paper describes a case study and design flow of a secure embedded system called ThumbPod, which uses cryptographic and biometric signal processing acceleration. It presents t...
David Hwang, Bo-Cheng Lai, Patrick Schaumont, Kazu...
DATE
2003
IEEE
86views Hardware» more  DATE 2003»
15 years 12 months ago
Layered, Multi-Threaded, High-Level Performance Design
A primary goal of high-level modeling is to efficiently explore a broad design space, converging on an optimal or near-optimal system architecture before moving to a more detaile...
Andrew S. Cassidy, JoAnn M. Paul, Donald E. Thomas