1342 search results - page 176 / 269 » MEMS Design And Verification |
159
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DAC
1999
ACM
16 years 7 months ago
1999
ACM
This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using Relative Timing. This method...
176
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DAC
2004
ACM
16 years 7 months ago
2004
ACM
Bounded Model Checking (BMC) relies on solving a sequence of highly correlated Boolean satisfiability (SAT) problems, each of which corresponds to the existence of counter-example...
154
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SIGSOFT
2008
ACM
16 years 7 months ago
2008
ACM
Synthesis of system configurations from a given set of features is an important and very challenging problem. This paper makes a step towards this goal by describing an efficient ...
179
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DAC
2003
ACM
15 years 11 months ago
2003
ACM
Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describe...
160
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EMSOFT
2004
Springer
15 years 10 months ago
2004
Springer
The Simulink/Stateflow toolset is an integrated suite enabling model-based design and has become popular in the automotive and aeronautics industries. We have previously developed...