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» MEMS Design And Verification
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ARTS
1997
Springer
15 years 10 months ago
The Verus Language: Representing Time Efficiently with BDDs
There have been significant advances on formal methods to verify complex systems recently. Nevertheless, these methods have not yet been accepted as a realistic alternative to the ...
Sérgio Vale Aguiar Campos, Edmund M. Clarke
EMSOFT
2008
Springer
15 years 8 months ago
Symbolic analysis for improving simulation coverage of Simulink/Stateflow models
Aimed at verifying safety properties and improving simulation coverage for hybrid systems models of embedded control software, we propose a technique that combines numerical simul...
Rajeev Alur, Aditya Kanade, S. Ramesh, K. C. Shash...
FM
2008
Springer
127views Formal Methods» more  FM 2008»
15 years 7 months ago
A Schedulerless Semantics of TLM Models Written in SystemC Via Translation into LOTOS
TLM (Transaction-Level Modeling) was introduced to cope with the increasing complexity of Systems-on-Chip designs by raising the modeling level. Currently, TLM is primarily used fo...
Olivier Ponsini, Wendelin Serwe
FORTE
2010
15 years 7 months ago
On Efficient Models for Model Checking Message-Passing Distributed Protocols
Abstract. The complexity of distributed algorithms, such as state machine replication, motivates the use of formal methods to assist correctness verification. The design of the for...
Péter Bokor, Marco Serafini, Neeraj Suri
DAGSTUHL
2006
15 years 7 months ago
A Framework for Analyzing Composition of Security Aspects
The methodology of aspect-oriented software engineering has been proposed to factor out concerns that are orthogonal to the core functionality of a system. In particular, this is a...
Jorge Fox, Jan Jürjens