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» MEMS Design And Verification
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ISSTA
2004
ACM
15 years 11 months ago
Faster constraint solving with subtypes
Constraints in predicate or relational logic can be translated into boolean logic and solved with a SAT solver. For faster solving, it is common to exploit the typing of predicate...
Jonathan Edwards, Daniel Jackson, Emina Torlak, Vi...
SI3D
2003
ACM
15 years 11 months ago
Incorporating dynamic real objects into immersive virtual environments
We present algorithms that enable virtual objects to interact with and respond to virtual representations, avatars, of real objects. These techniques allow dynamic real objects, s...
Benjamin Lok, Samir Naik, Mary C. Whitton, Frederi...
SIGSOFT
2003
ACM
15 years 11 months ago
Fluent model checking for event-based systems
Model checking is an automated technique for verifying that a system satisfies a set of required properties. Such properties are typically expressed as temporal logic formulas, in...
Dimitra Giannakopoulou, Jeff Magee
ASPDAC
2007
ACM
82views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Efficient BMC for Multi-Clock Systems with Clocked Specifications
- Current industry trends in system design -- multiple clocks, clocks with arbitrary frequency ratios, multi-phased clocks, gated clocks, and level-sensitive latches, combined with...
Malay K. Ganai, Aarti Gupta
CAISE
2009
Springer
15 years 10 months ago
Data-Flow Anti-patterns: Discovering Data-Flow Errors in Workflows
Despite the abundance of analysis techniques to discover control-flow errors in workflow designs, there is hardly any support for w verification. Most techniques simply abstract fr...
Nikola Trcka, Wil M. P. van der Aalst, Natalia Sid...