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ITC
2003
IEEE
113views Hardware» more  ITC 2003»
15 years 11 months ago
Fault Injection for Verifying Testability at the VHDL Level
This paper presents a technique to improve verification at the VHDL level of digital circuits by means of a specially designed fault injection block. The injection technique allow...
S. R. Seward, Parag K. Lala
DAC
1998
ACM
16 years 7 months ago
Combining Theorem Proving and Trajectory Evaluation in an Industrial Environment
We describe the verification of the IM: a large, complex (12,000 gates and 1100 latches) circuit that detects and marks the boundaries between Intel architecture (IA-32) instructi...
Mark Aagaard, Robert B. Jones, Carl-Johan H. Seger
CSCWD
2009
Springer
16 years 1 months ago
Random stimulus generation with self-tuning
Constrained random simulation methodology still plays an important role in hardware verification due to the limited scalability of formal verification, especially for the large an...
Yanni Zhao, Jinian Bian, Shujun Deng, Zhiqiu Kong
EDOC
2000
IEEE
15 years 10 months ago
Model Checking of Workflow Schemas
Practical experience indicates that the definition of realworld workflow applications is a complex and error-prone process. Existing workflow management systems provide the means,...
Christos T. Karamanolis, Dimitra Giannakopoulou, J...
DATE
2004
IEEE
174views Hardware» more  DATE 2004»
15 years 10 months ago
Graph-Based Functional Test Program Generation for Pipelined Processors
Functional verification is widely acknowledged as a major bottleneck in microprocessor design. While early work on specification driven functional test program generation has prop...
Prabhat Mishra, Nikil Dutt