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» Low power techniques for Motion Estimation hardware
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ASPDAC
2001
ACM
83views Hardware» more  ASPDAC 2001»
15 years 9 months ago
Trace-driven system-level power evaluation of system-on-a-chip peripheral cores
Our earlier work for fast evaluation of power consumption of general cores in a system-on-a-chip described techniques that involved isolating high-level instructions of a core, me...
Tony Givargis, Frank Vahid, Jörg Henkel
APCCAS
2006
IEEE
272views Hardware» more  APCCAS 2006»
16 years 7 days ago
Power Analysis for the MOS AC/DC Rectifier of Passive RFID Transponders
—The operating principle of MOS FETs AC/DC rectifier for passive RFID transponder is introduced and the power dissipation of MOS rectifier operating with 902M-928MHz industrial, ...
Changming Ma, Chun Zhang, Zhihua Wang
ICASSP
2010
IEEE
15 years 6 months ago
High order motion interpolation for side information improvement in DVC
A key step in distributed video coding is the generation of the side information (SI) i.e. the estimation of the Wyner-Ziv frame (WZF). This step is also frequently called image i...
Giovanni Petrazzuoli, Marco Cagnazzo, Béatr...
ASPDAC
2006
ACM
159views Hardware» more  ASPDAC 2006»
16 years 5 days ago
Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology
: With technology scaling, elevated temperatures caused by increased power density create a critical bottleneck modulating the circuit operation. With the advent of FinFET technolo...
Aditya Bansal, Mesut Meterelliyoz, Siddharth Singh...
ICCD
2004
IEEE
98views Hardware» more  ICCD 2004»
16 years 3 months ago
Coping with The Variability of Combinational Logic Delays
Abstract— This paper proposes a technique for creating a combinational logic network with an output that signals when all other outputs have stabilized. The method is based on du...
Jordi Cortadella, Alex Kondratyev, Luciano Lavagno...