Sciweavers

552 search results - page 45 / 111
» Low power techniques for Motion Estimation hardware
Sort
View
ISQED
2008
IEEE
118views Hardware» more  ISQED 2008»
16 years 16 days ago
A Thermal-Friendly Load-Balancing Technique for Multi-Core Processors
In multi-core processors there are several ways to pair a thread to a particular core. These load-balancing techniques result in a quite different power, performance and thermal b...
Enric Musoll
ASPDAC
2006
ACM
104views Hardware» more  ASPDAC 2006»
15 years 10 months ago
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar proces
- Technology scaling and sub-wavelength optical lithography is associated with significant process variations. We propose a self-adaptive variable supply-voltage scaling (SAVS) tec...
Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh
ISLPED
1995
ACM
116views Hardware» more  ISLPED 1995»
15 years 9 months ago
Activity-sensitive architectural power analysis for the control path
Prompted by demands for portability and low-cost packaging, the electronics industry has begun to view power consumption as a critical design criteria. As such there is a growing ...
Paul E. Landman, Jan M. Rabaey
DATE
1999
IEEE
112views Hardware» more  DATE 1999»
15 years 10 months ago
Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach
Estimating switching activity is a crucial step in optimizing circuits for low power. In this paper, a fast gate level switching activity estimator for combinational circuits will...
Markus Bühler, Matthias Papesch, K. Kapp, Utz...
FCCM
2006
IEEE
162views VLSI» more  FCCM 2006»
16 years 6 days ago
Power Visualization, Analysis, and Optimization Tools for FPGAs
This paper introduces the Low-Power Intelligent Tool Environment (LITE), an object oriented tool set designed for power visualization, analysis, and optimization. These tools lever...
Matthew French, Li Wang, Michael J. Wirthlin