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» Low power architecture of the soft-output Viterbi algorithm
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ICCAD
2002
IEEE
113views Hardware» more  ICCAD 2002»
16 years 2 months ago
Interconnect-aware high-level synthesis for low power
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
Lin Zhong, Niraj K. Jha
NOMS
2006
IEEE
16 years 14 hour ago
System Support for Management of Networked Low-Power Sensors
— This paper addresses the problem of managing a wireless sensor network with mobile managers. The mobile managers should be able to create their connectivity to the nodes they m...
Jai-Jin Lim, Daniel L. Kiskis, Kang G. Shin
DAC
2009
ACM
16 years 7 months ago
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications
Power consumption of system-level on-chip communications is becoming more significant in the overall system-on-chip (SoC) power as technology scales down. In this paper, we propos...
Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-K...
ICMCS
2005
IEEE
123views Multimedia» more  ICMCS 2005»
15 years 11 months ago
Nearly Lossless Content-Dependent Low-Power DCT Design for Mobile Video Applications
This paper proposes a practical content-dependent lowpower DCT design with tolerable quality drop. Lowpower issue has become more and more important, especially for portable devic...
Chia-Ping Lin, Po-Chih Tseng, Liang-Gee Chen
DAC
1999
ACM
15 years 10 months ago
Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications
Dual threshold technique has been proposed to reduce leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical p...
Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye,...