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MICRO
2006
IEEE
144views Hardware» more  MICRO 2006»
16 years 12 days ago
Die Stacking (3D) Microarchitecture
3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die ...
Bryan Black, Murali Annavaram, Ned Brekelbaum, Joh...
IPCCC
2006
IEEE
16 years 12 days ago
OS-aware tuning: improving instruction cache energy efficiency on system workloads
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
Tao Li, Lizy K. John
HPCA
2009
IEEE
16 years 7 months ago
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Magnetic Random Access Memory (MRAM) is considered to be a promising future memory technology due to its low leakage power, high density and fast read speed. The heterogeneous int...
Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yira...
SIGCOMM
2010
ACM
15 years 6 months ago
Accelerating SSL with GPUs
SSL/TLS is a standard protocol for secure Internet communication. Despite its great success, today's SSL deployment is largely limited to security-critical domains. The low a...
Keon Jang, Sangjin Han, Seungyeop Han, Sue B. Moon...
ISCAS
2006
IEEE
74views Hardware» more  ISCAS 2006»
16 years 12 days ago
Low-power hybrid turbo decoding based on reverse calculation
—As turbo decoding is a highly memory-intensive algorithm consuming large power, a major issue to be solved in practical implementation is to reduce power consumption. This paper...
Hye-Mi Choi, Ji-Hoon Kim, In-Cheol Park