1307 search results - page 167 / 262 » Low Power Hardware for a High Performance PDA |
142
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DATE
2007
IEEE
16 years 22 days ago
2007
IEEE
Because of its excellent bit-error-rate performance, the Low-Density Parity-Check (LDPC) decoding algorithm is gaining increased attention in communication standards and literatur...
147
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DATE
2007
IEEE
16 years 22 days ago
2007
IEEE
RFIC reliability is fast becoming a major bottleneck in the yield and performance of modern IC systems, as process complexity and levels of integration continually increase. Due t...
DATE
2006
IEEE
16 years 14 days ago
2006
IEEE
In this paper we present an overview of an on-chip noise detection circuit. Mainly, this work is different form the previous works concerning on-chip noise measurement in one or m...
142
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DATE
2003
IEEE
15 years 11 months ago
2003
IEEE
In Networks on Chip, NoC, very low cost and high performance switches will be of critical importance. For a regular two-dimensional NoC we propose a very simple, memoryless switch...
155
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ICASSP
2011
IEEE
14 years 10 months ago
2011
IEEE
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...