1307 search results - page 163 / 262 » Low Power Hardware for a High Performance PDA |
152
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IPPS
2005
IEEE
16 years 3 hour ago
2005
IEEE
A new high performance computation technique involving multiple processors on a single silicon die is quickly gaining popularity. This new design approach provides very high perfo...
260
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DATE
2011
IEEE
14 years 10 months ago
2011
IEEE
Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case...
175
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CHES
2005
Springer
15 years 12 months ago
2005
Springer
Two new FPGA designs for the Advanced Encryption Standard (AES) are presented. The first is believed to be the fastest, achieving 25 Gbps throughput using a Xilinx Spartan-III (XC3...
177
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ISPDC
2007
IEEE
16 years 21 days ago
2007
IEEE
The task management is a key point in grid applications and can highly influence their efficiency. There are many solutions that we can classify according to their centralizatio...
185
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CODES
2007
IEEE
16 years 23 days ago
2007
IEEE
This article presents a multiprocessor system-on-chip synthesis (MPSoC) algorithm that optimizes system mean time to failure. Given a set of directed acyclic periodic graphs of co...