1307 search results - page 156 / 262 » Low Power Hardware for a High Performance PDA |
141
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ARC
2009
Springer
15 years 11 months ago
2009
Springer
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...
165
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APCCAS
2006
IEEE
16 years 15 days ago
2006
IEEE
—A method of embedding data in a JPEG color image for applications such as authentication of an employee carrying a picture identification card is described. Embedding of data, s...
192
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ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustne...
165
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MICRO
2000
IEEE
15 years 6 months ago
2000
IEEE
High-performance microprocessors are currently designed to exploit the inherent instruction level parallelism (ILP) available in most applications. The techniques used in their de...
174
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MICRO
2009
IEEE
16 years 1 months ago
2009
IEEE
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...