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ASPDAC
1995
ACM
127views Hardware» more  ASPDAC 1995»
15 years 10 months ago
Reclocking for high-level synthesis
In this paper we describe, a powerful post-synthesis approach called reclocking, for performance improvement by minimizing the total execution time. By back annotating the wire del...
Pradip K. Jha, Nikil D. Dutt, Sri Parameswaran
CF
2005
ACM
15 years 8 months ago
An efficient wakeup design for energy reduction in high-performance superscalar processors
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
Kuo-Su Hsiao, Chung-Ho Chen
DPHOTO
2009
116views Hardware» more  DPHOTO 2009»
15 years 4 months ago
Interleaved imaging: an imaging system design inspired by rod-cone vision
Under low illumination conditions, such as moonlight, there simply are not enough photons present to create a high quality color image with integration times that avoid camera-sha...
Manu Parmar, Brian A. Wandell
JSA
2006
167views more  JSA 2006»
15 years 6 months ago
Pattern-driven prefetching for multimedia applications on embedded processors
Multimedia applications in general and video processing, such as the MPEG4 Visual stream decoders, in particular are increasingly popular and important workloads for future embedd...
Hassan Sbeyti, Smaïl Niar, Lieven Eeckhout
TPDS
2010
109views more  TPDS 2010»
15 years 4 months ago
Thermal-Aware Task Scheduling for 3D Multicore Processors
Abstract—A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, highspeed interface to increase the device den...
Xiuyi Zhou, Jun Yang 0002, Yi Xu, Youtao Zhang, Ji...