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DAC
1997
ACM
15 years 10 months ago
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha C...
RTSS
1993
IEEE
15 years 10 months ago
Object-Based Semantic Real-Time Concurrency Control
This paper presents a technique that is capable of supporting two major requirements for concurrency control in real-time databases: data temporal consistency, and data logical co...
Lisa Cingiser DiPippo, Victor Fay Wolfe
AHS
2007
IEEE
211views Hardware» more  AHS 2007»
15 years 10 months ago
Synthesis of Multimode digital signal processing systems
In this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. The inputs of...
Caaliph Andriamisaina, Emmanuel Casseau, Philippe ...
DATE
2004
IEEE
144views Hardware» more  DATE 2004»
15 years 10 months ago
Smaller Two-Qubit Circuits for Quantum Communication and Computation
We show how to implement an arbitrary two-qubit unitary operation using any of several quantum gate libraries with small a priori upper bounds on gate counts. In analogy to librar...
Vivek V. Shende, Igor L. Markov, Stephen S. Bulloc...
EMSOFT
2006
Springer
15 years 10 months ago
A superblock-based flash translation layer for NAND flash memory
In NAND flash-based storage systems, an intermediate software layer called a flash translation layer (FTL) is usually employed to hide the erase-before-write characteristics of NA...
Jeong-Uk Kang, Heeseung Jo, Jinsoo Kim, Joonwon Le...