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ISCA
1998
IEEE
125views Hardware» more  ISCA 1998»
15 years 10 months ago
Active Pages: A Computation Model for Intelligent Memory
Microprocessors and memory systems su er from a growing gap in performance. We introduce Active Pages, a computation model which addresses this gap by shifting data-intensive comp...
Mark Oskin, Frederic T. Chong, Timothy Sherwood
ISSS
1998
IEEE
96views Hardware» more  ISSS 1998»
15 years 10 months ago
Fine Grain Incremental Rescheduling Via Architectural Retiming
With the decreasing feature sizes during VLSI fabrication and the dominance of interconnect delay over that of gates, control logic and wiring no longer have a negligible impact o...
Soha Hassoun
KBSE
1998
IEEE
15 years 10 months ago
Towards the Automated Debugging and Maintenance of Logic-based Requirements Models
In this paper we describe a tools environment which automates the validation and maintenance of a requirements model written in many-sorted first order logic. We focus on: a trans...
T. L. McCluskey, Margaret Mary West
AMAST
1998
Springer
15 years 10 months ago
Type Analysis for CHIP
Abstract. This paper proposes a tool to support reasoning about (partial) correctness of constraint logic programs. The tool infers a speci cation that approximates the semantics o...
Wlodzimierz Drabent, Pawel Pietrzak
FPGA
1998
ACM
148views FPGA» more  FPGA 1998»
15 years 10 months ago
Configuration Prefetch for Single Context Reconfigurable Coprocessors
Current reconfigurable systems suffer from a significant overhead due to the time it takes to reconfigure their hardware. In order to deal with this overhead, and increase the com...
Scott Hauck