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FM
2003
Springer
98views Formal Methods» more  FM 2003»
15 years 11 months ago
Generating Counterexamples for Multi-valued Model-Checking
Counterexamples explain why a desired temporal logic property fails to hold, and as such are considered to be the most useful form of output from model-checkers. Multi-valued model...
Arie Gurfinkel, Marsha Chechik
FM
2003
Springer
174views Formal Methods» more  FM 2003»
15 years 11 months ago
Model-Checking TRIO Specifications in SPIN
We present a novel application on model checking through SPIN as a means for verifying purely descriptive specifications written in TRIO, a first order, linear-time temporal logic ...
Angelo Morzenti, Matteo Pradella, Pierluigi San Pi...
ISMVL
2010
IEEE
191views Hardware» more  ISMVL 2010»
15 years 11 months ago
Toffoli Gate Implementation Using the Billiard Ball Model
— In this paper we review the Billiard Ball Model (BBM) introduced by Toffoli and Fredkin. The analysis of a previous approach to design reversible networks based on BBM it shown...
Hadi Hosseini, Gerhard W. Dueck
ASAP
2002
IEEE
103views Hardware» more  ASAP 2002»
15 years 11 months ago
PAPA - Packed Arithmetic on a Prefix Adder for Multimedia Applications
This paper introduces PAPA: Packed Arithmetic on a Prefix Adder, a new approach to parallel prefix adder design that supports a wide variety of packed arithmetic computations, inc...
Neil Burgess
ITC
2002
IEEE
81views Hardware» more  ITC 2002»
15 years 11 months ago
Design Rewiring Using ATPG
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri