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IEEEPACT
1999
IEEE
15 years 11 months ago
A Cost-Effective Clustered Architecture
In current superscalar processors, all floating-point resources are idle during the execution of integer programs. As previous works show, this problem can be alleviated if the fl...
Ramon Canal, Joan-Manuel Parcerisa, Antonio Gonz&a...
CONCUR
1999
Springer
15 years 11 months ago
Partial Order Reduction for Model Checking of Timed Automata
Abstract. The paper presents a partial order reduction method applicable to networks of timed automata. The advantage of the method is that it reduces both the number of explored c...
Marius Minea
TPHOL
1999
IEEE
15 years 11 months ago
Isar - A Generic Interpretative Approach to Readable Formal Proof Documents
Abstract. We present a generic approach to readable formal proof documents, called Intelligible semi-automated reasoning (Isar). It addresses the major problem of existing interact...
Markus Wenzel
MICRO
1998
IEEE
91views Hardware» more  MICRO 1998»
15 years 11 months ago
Effective Cluster Assignment for Modulo Scheduling
Clustering is one solution to the demand for wideissue machines and fast clock cycles because it allows for smaller, less ported register files and simpler bypass logic while rema...
Erik Nystrom, Alexandre E. Eichenberger
FPL
1998
Springer
86views Hardware» more  FPL 1998»
15 years 10 months ago
Self Modifying Circuitry - A Platform for Tractable Virtual Circuitry
The readily available performance advantages, gained in early virtual circuitry systems, are being recouped following advances in general purpose processor architectures and have ...
Adam Donlin