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FPGA
2001
ACM
145views FPGA» more  FPGA 2001»
15 years 11 months ago
Simultaneous logic decomposition with technology mapping in FPGA designs
Conventional technology mapping algorithms for SRAM-based Field Programmable Gate Arrays (FPGAs) are normally carried out on a fixed logic decomposition of a circuit. The impact o...
Gang Chen, Jason Cong
ICLP
2010
Springer
15 years 10 months ago
Tabling and Answer Subsumption for Reasoning on Logic Programs with Annotated Disjunctions
Probabilistic Logic Programming is an active field of research, with many proposals for languages, semantics and reasoning algorithms. One such proposal, Logic Programming with A...
Fabrizio Riguzzi, Terrance Swift
ICCAD
1995
IEEE
88views Hardware» more  ICCAD 1995»
15 years 10 months ago
LOT: logic optimization with testability-new transformations using recursive learning
: A new approach to optimize multi-level logic circuits is introduced. Given a multi-level circuit, the synthesis method optimizes its area, simultaneously enhancing its random pat...
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang K...
CORR
2008
Springer
121views Education» more  CORR 2008»
15 years 6 months ago
Separability in the Ambient Logic
Abstract. The Ambient Logic (AL) has been proposed for expressing properties of process mobility in the calculus of Mobile Ambients (MA), and as a basis for query languages on semi...
Daniel Hirschkoff, Étienne Lozes, Davide Sa...
ET
2010
98views more  ET 2010»
15 years 5 months ago
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics
Abstract As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to...
Stephan Eggersglüß, Görschwin Fey,...