A formal framework for software development and analysis is presented, which aims at reducing the gap between formal specification and implementation by integrating the two and al...
The argument against ASIC SoCs is that they have always taken too long and cost too much to design. As new process technologies come on line, the issue of inflexible, unyielding d...
J. Bryan Lewis, Ivo Bolsens, Rudy Lauwereins, Chri...
This paper details the development, implementation, and results of Synthia, a system for the synthesis of Finite State Machines (FSMs) to field-programmable logic. Our approach us...
George A. Constantinides, Peter Y. K. Cheung, Wayn...
The paper argues, that a direct formalization of the way common sense thinks about the numerical identity of enduring entities, requires that traditional predicate logic is develo...
We study the automated verification of pointer safety for heap-manipulating imperative programs with unknown procedure calls. Given a Hoare-style partial correctness specificati...