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ISCAS
2005
IEEE
224views Hardware» more  ISCAS 2005»
16 years 6 days ago
A high-speed domino CMOS full adder driven by a new unified-BiCMOS inverter
— A new operation mode using a partially depleted hybrid lateral BJT-CMOS inverter on SOI, named as a new unified-BiCMOS (U-BiCMOS) inverter, is proposed. The scheme utilizes the...
Toshiro Akino, Kei Matsuura, Akiyoshi Yasunaga
ISCAS
2005
IEEE
173views Hardware» more  ISCAS 2005»
16 years 6 days ago
CMOS contact imager for monitoring cultured cells
— There is a growing interest in developing low cost, low power, highly integrated biosensor systems to characterize individual cells for applications such as cell analysis, drug...
Honghao Ji, Pamela Abshire, M. Urdaneta, Elisabeth...
ISDA
2005
IEEE
16 years 6 days ago
Hybrid Fuzzy-Genetic Algorithm Approach for Crew Grouping
Crew grouping is an important problem and formulating a good solution always involves many challenges. For example, grouping soldiers intelligently to tank combat units, we should...
Hongbo Liu, Zhanguo Xu, Ajith Abraham
TIME
2005
IEEE
16 years 6 days ago
LOLA: Runtime Monitoring of Synchronous Systems
Abstract— We present a specification language and algorithms for the online and offline monitoring of synchronous systems including circuits and embedded systems. Such monitori...
Ben D'Angelo, Sriram Sankaranarayanan, Césa...
ASPDAC
2005
ACM
127views Hardware» more  ASPDAC 2005»
16 years 6 days ago
Clock network minimization methodology based on incremental placement
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...
Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, ...