9532 search results - page 447 / 1907 » Logic, Graphs, and Algorithms |
177
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GLVLSI
2008
IEEE
16 years 1 months ago
2008
IEEE
Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves “shortening” all paths found in the circ...
180
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MFCS
1998
Springer
15 years 11 months ago
1998
Springer
It is known that a language is context-free iff it is the set of borders of the trees of recognizable set, where the border of a (labelled) tree is the word consisting of its leaf ...
173
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FPGA
2001
ACM
15 years 11 months ago
2001
ACM
Conventional technology mapping algorithms for SRAM-based Field Programmable Gate Arrays (FPGAs) are normally carried out on a fixed logic decomposition of a circuit. The impact o...
188
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AAAI
2008
15 years 9 months ago
2008
Markov logic networks (MLNs) combine first-order logic and Markov networks, allowing us to handle the complexity and uncertainty of real-world problems in a single consistent fram...
155
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ICLP
1995
Springer
15 years 10 months ago
1995
Springer
The purpose of this paper is to study the problem of complete type inferencing for polymorphic order-sorted logic programs. We show that previous approaches are incomplete even if...