9532 search results - page 1672 / 1907 » Logic, Graphs, and Algorithms |
169
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DAC
2002
ACM
16 years 7 months ago
2002
ACM
A central problem in functional verification is to check that a circuit block is producing correct outputs while enforcing that the environment is providing legal inputs. To attac...
172
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DAC
2003
ACM
16 years 7 months ago
2003
ACM
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or...
166
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DAC
2004
ACM
16 years 7 months ago
2004
ACM
A modular synthesis flow is essential for a scalable and hierarchical design methodology. This paper considers a particular modular flow where each module has interface methods an...
189
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DAC
2004
ACM
16 years 7 months ago
2004
ACM
Bounded Model Checking (BMC) relies on solving a sequence of highly correlated Boolean satisfiability (SAT) problems, each of which corresponds to the existence of counter-example...
164
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and dela...