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FPGA
2007
ACM
163views FPGA» more  FPGA 2007»
16 years 24 days ago
Improved SAT-based Boolean matching using implicants for LUT-based FPGAs
Boolean matching (BM) is a widely used technique in FPGA resynthesis and architecture evaluation. In this paper we present several improvements to the recently proposed SAT-based ...
Jason Cong, Kirill Minkovich
SPIN
2007
Springer
16 years 23 days ago
Tutorial: Parallel Model Checking
d Abstract) Luboˇs Brim and Jiˇr´ı Barnat Faculty of Informatics, Masaryk University, Brno, Czech Republic With the increase in the complexity of computer systems, it becomes e...
Lubos Brim, Jiri Barnat
DATE
2006
IEEE
158views Hardware» more  DATE 2006»
16 years 21 days ago
Modeling multiple input switching of CMOS gates in DSM technology using HDMR
Abstract— Continuing scaling of CMOS technology has allowed aggressive pursuant of increased clock rate in DSM chips. The ever shorter clock period has made switching times of di...
Jayashree Sridharan, Tom Chen
DOCENG
2006
ACM
16 years 19 days ago
Comparing XML path expressions
XPath is the standard declarative language for navigating XML data and returning a set of matching nodes. In the context of XSLT/XQuery analysis, query optimization, and XML type ...
Pierre Genevès, Nabil Layaïda
EVOW
2001
Springer
15 years 11 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...
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