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DDECS
2007
IEEE
175views Hardware» more  DDECS 2007»
16 years 1 months ago
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
—An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with sp...
Philipp Öhler, Sybille Hellebrand, Hans-Joach...
ISCAS
2006
IEEE
122views Hardware» more  ISCAS 2006»
16 years 24 days ago
256-channel integrated neural interface and spatio-temporal signal processor
Abstract- We present an architecture and VLSI implemen- Various strategies in the analysis of spatio-temporal dynamtation of a distributed neural interface and spatio-temporal ics ...
J. N. Y. Aziz, Roman Genov, B. R. Bardakjian, M. D...
SIGSOFT
2004
ACM
16 years 6 days ago
Correlation exploitation in error ranking
Static program checking tools can find many serious bugs in software, but due to analysis limitations they also frequently emit false error reports. Such false positives can easi...
Ted Kremenek, Ken Ashcraft, Junfeng Yang, Dawson R...
169
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ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Node Mergers in the Presence of Don't Cares
Abstract-- SAT sweeping is the process of merging two or more functionally equivalent nodes in a circuit by selecting one of them to represent all the other equivalent nodes. This ...
Stephen Plaza, Kai-Hui Chang, Igor L. Markov, Vale...
JBI
2004
171views Bioinformatics» more  JBI 2004»
15 years 8 months ago
Consensus Clustering and Functional Interpretation of Gene Expression Data
Microarray analysis using clustering algorithms can suffer from lack of inter-method consistency in assigning related gene-expression profiles to clusters. Obtaining a consensus s...
Paul Kellam, Stephen Swift, Allan Tucker, Veronica...
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