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HPCN
2000
Springer
15 years 10 months ago
An Analytical Model for a Class of Architectures under Master-Slave Paradigm
We build an analytical model for an application utilizing master-slave paradigm. In the model, only three architecture parameters are used: latency, bandwidth and flop rate. Instea...
Yasemin Yalçinkaya, Trond Steihaug
ISCAS
2008
IEEE
115views Hardware» more  ISCAS 2008»
16 years 26 days ago
Adaptive delay compensation in multi-dithering adaptive control
Abstract— Recently, a delay-insensitive architecture for gradient descent adaptive control, based on parallel synchronous detection for model-free gradient estimation was present...
Dimitrios N. Loizos, Paul-Peter Sotiriadis, Gert C...
ICC
2007
IEEE
254views Communications» more  ICC 2007»
15 years 10 months ago
Group Rekeying Schemes for Secure Group Communication in Wireless Sensor Networks
Wireless sensor networks are promising solutions for many applications. However, wireless sensor nodes suffer from many constraints such as low computation capability, small memory...
Yong Wang, Byrav Ramamurthy
EURODAC
1995
IEEE
133views VHDL» more  EURODAC 1995»
15 years 10 months ago
Tree restructuring approach to mapping problem in cellular-architecture FPGAs
A new technique for mapping combinational circuits to Fine-Grain Cellular-Architecture FPGAs is presented. The proposed tree restructuring algorithm preserves local connectivity a...
Naveen Ramineni, Malgorzata Chrzanowska-Jeske, Nav...
ISSS
1995
IEEE
96views Hardware» more  ISSS 1995»
15 years 10 months ago
Time-constrained code compaction for DSPs
{DSP algorithms in most cases are subject to hard real-time constraints. In case of programmable DSP processors, meeting those constraints must be ensured by appropriate code gener...
Rainer Leupers, Peter Marwedel