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» Load-Reuse Analysis: Design and Evaluation
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GLVLSI
2007
IEEE
194views VLSI» more  GLVLSI 2007»
15 years 10 months ago
Probabilistic maximum error modeling for unreliable logic circuits
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
Karthikeyan Lingasubramanian, Sanjukta Bhanja
ESA
2006
Springer
140views Algorithms» more  ESA 2006»
15 years 9 months ago
Latency Constrained Aggregation in Sensor Networks
A sensor network consists of sensing devices which may exchange data through wireless communication. A particular feature of sensor networks is that they are highly energy constrai...
Luca Becchetti, Peter Korteweg, Alberto Marchetti-...
IEAAIE
2000
Springer
15 years 9 months ago
Maintenance of KBS's by Domain Experts: The Holy Grail in Practice
Enabling a domain expert to maintain his own knowledge in a Knowledge Based System has long been an ideal for the Knowledge Engineering community. In this paper we report on our ex...
Arne Bultmann, Joris Kuipers, Frank van Harmelen
USENIX
2008
15 years 8 months ago
Idle Read After Write - IRAW
Despite a low occurrence rate, silent data corruption represents a growing concern for storage systems designers. Throughout the storage hierarchy, from the file system down to th...
Alma Riska, Erik Riedel
CCS
2008
ACM
15 years 8 months ago
Towards an efficient and language-agnostic compliance checker for trust negotiation systems
To ensure that a trust negotiation succeeds whenever possible, authorization policy compliance checkers must be able to find all minimal sets of their owners' credentials tha...
Adam J. Lee, Marianne Winslett