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FORMATS
2006
Springer
15 years 10 months ago
Timed Alternating-Time Temporal Logic
We add freeze quantifiers to the game logic ATL in order to specify real-time objectives for games played on timed structures. We define the semantics of the resulting logic TATL b...
Thomas A. Henzinger, Vinayak S. Prabhu
ICCD
1991
IEEE
65views Hardware» more  ICCD 1991»
15 years 10 months ago
Self-Timed Logic Using Current-Sensing Completion Detection (CSCD)
This article proposes a completion-detection method for efficiently implementing Boolean functions as self-timed logic structures. Current-Sensing Completion Detection, CSCD, allow...
Mark E. Dean, David L. Dill, Mark Horowitz
ICCD
1993
IEEE
111views Hardware» more  ICCD 1993»
15 years 10 months ago
Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
Michael A. Riepe, João P. Marques Silva, Ka...
ACL
2006
15 years 8 months ago
Translating HPSG-Style Outputs of a Robust Parser into Typed Dynamic Logic
The present paper proposes a method by which to translate outputs of a robust HPSG parser into semantic representations of Typed Dynamic Logic (TDL), a dynamic plural semantics de...
Manabu Sato, Daisuke Bekki, Yusuke Miyao, Jun-ichi...
COMPGEOM
2004
ACM
16 years 1 days ago
On the least median square problem
We consider the exact and approximate computational complexity of the multivariate LMS linear regression estimator. The LMS estimator is among the most widely used robust linear s...
Jeff Erickson, Sariel Har-Peled, David M. Mount